When India's Union Cabinet approved the IndiaAI Mission in March 2024, with a total outlay of ₹10,372 crore, the largest single component of that money was earmarked for one purpose: building a shared national pool of GPU compute so that Indian startups, researchers, and government labs would not have to rent every hour of training time from a handful of foreign clouds. But the chips India needed to buy were not something Nvidia, or anyone else, could simply agree to sell more of. Every H100 or A100 destined for that compute pool is designed by a company headquartered in California, fabricated almost entirely by one foundry in Taiwan, and export-licensed under a rule written by the US Department of Commerce's Bureau of Industry and Security (BIS): a rule that decides, chip model by chip model, whether that GPU may leave the country where it was made at all. India was never the rule's intended target; China was. But because the rule classifies hardware rather than naming countries, it reshaped a compute market that a nation of 1.4 billion people depends on for an AI strategy it wrote for itself.
That is what "AI geopolitics" looks like in practice: not diplomats debating AI ethics at a summit podium, but a semiconductor export-control clause deciding which countries train frontier models on schedule, and which wait in a queue they do not control. This chapter builds the technical and strategic machinery to understand that clause, and the wider contest it belongs to, from first principles.
The AI triad: why compute became the strategic chokepoint
Strategic competition over AI capability is easiest to reason about through a decomposition that Georgetown's Center for Security and Emerging Technology (CSET) formalized in 2020. In The AI Triad and What It Means for National Security Strategy, Ben Buchanan argued that any AI system's capability is a function of three inputs: compute (the hardware that runs training and inference), data (the examples a model learns from), and algorithms (the architectures and training techniques researchers publish). Governments concerned with AI's strategic implications eventually have to choose one of these three as their point of leverage, because the three inputs are not equally governable.
Data is hard to control at a national scale. It is non-rival (your using a dataset does not stop me from using a copy of it), cheap to duplicate, and often scraped from a public internet that respects no border. Algorithms are, if anything, a worse target for control: the core ideas behind transformer attention, mixture-of-experts routing, or RLHF fine-tuning are published in papers, implemented in open-source repositories, and move between labs and countries at the speed of a PDF download or a researcher changing employers.
Compute is different, and the difference is physical. A GPU capable of training a frontier model is a manufactured, serialized, trackable object, built through one of the most capital-intensive and geographically concentrated supply chains in industrial history. You cannot email a wafer. This is why, starting in October 2022, the principal US lever for shaping the pace of Chinese frontier-AI development has not been a rule about algorithms or a rule about training data. It has been a rule about chips.
The physical chokepoint: three firms gate the world's advanced AI silicon
Three stages sit between a chip design and a working AI accelerator, and each is dominated by a small number of firms concentrated in a small number of countries. First, the electronic design automation (EDA) software and processor instruction-set IP used to design the chip: dominated by Synopsys, Cadence, and Arm, all headquartered in the US or UK. Second, extreme ultraviolet (EUV) lithography, the technique needed to pattern transistors below roughly the 7-nanometre node: exactly one company in the world, ASML of the Netherlands, builds EUV scanners, and it does not sell them into China. Third, fabrication itself, the process of turning a finished design into physical silicon at leading-edge nodes: that capacity is overwhelmingly concentrated at TSMC in Taiwan, which fabricates the large majority of the world's sub-7nm logic chips, including essentially all of Nvidia's data-centre GPUs.
None of this concentration exists because of export-control policy. It exists because lithography, chip-design tooling, and leading-edge fabrication each carry enormous economies of scale and decades of accumulated, hard-to-replicate process knowledge; a single EUV scanner costs on the order of hundreds of millions of dollars and takes months to install and calibrate. Export control exploits a chokepoint that industrial economics already built; it did not create the chokepoint. That is also why the chokepoint is so hard to route around: unlike a tariff, which a buyer can simply pay, an export licence you are refused is a wall, not a price.
The diagram below traces this pipeline end to end, including the decision gate a finished chip must clear before it can legally be exported toward a restricted destination.
Worked example: how an export-control threshold actually decides a chip's fate
The gate in the diagram is not a metaphor; it is arithmetic BIS wrote into the Export Administration Regulations under ECCN 3A090. The controlling metric is called Total Processing Performance (TPP), and it is defined as twice the chip's peak multiply-accumulate throughput (in tera-operations per second, TOPS — the datasheet number already counts each multiply-accumulate as two operations) multiplied by the bit length of the operation, summed across every processing unit on the die. Because chip datasheets already report throughput using the "one multiply-accumulate counts as two operations" convention, this collapses to a simpler working rule: TPP equals the datasheet's dense (non-sparse) throughput number, multiplied by the bit width of that number.
A chip is controlled for restricted destinations if TPP is at least 4,800, or if TPP is at least 1,600 and performance density (PD, defined as TPP divided by die area in mm², a proxy for how much compute is packed into a physically exportable object) is at least 5.92. Let's run the Nvidia A100 (the GA100 die, fabricated by TSMC on its N7 process, with a die area of 826 mm²) through the gate.
def tpp(dense_throughput, bit_length):
"""dense_throughput: datasheet dense TOPS/TFLOPS (no sparsity boost)
bit_length: precision width of that operation, in bits
Returns Total Processing Performance per BIS ECCN 3A090."""
return dense_throughput * bit_length
# NVIDIA A100 (GA100), TSMC N7, 826 mm^2 die
tpp_int8 = tpp(624, 8) # dense INT8 Tensor Core: 624 TOPS
tpp_fp16 = tpp(312, 16) # dense FP16 Tensor Core: 312 TFLOPS
THRESHOLD_TPP = 4800
DIE_AREA_MM2 = 826
PD = tpp_int8 / DIE_AREA_MM2
print(tpp_int8, tpp_fp16, tpp_int8 > THRESHOLD_TPP, round(PD, 2))Trace it by hand before trusting the printout. Dense INT8 throughput is 624 TOPS at 8-bit width, so tpp_int8 = 624 × 8 = 4,992. Dense FP16 throughput is 312 TFLOPS at 16-bit width, so tpp_fp16 = 312 × 16 = 4,992: the same number, and not by coincidence. A Tensor Core's multiply-accumulate array is a fixed budget of transistors; halving the bit width of each operand roughly doubles how many operations fit in the same silicon per cycle, so throughput and bit width trade off almost exactly, and their product stays close to invariant across precisions. That is a genuine hardware-design regularity, and it is exactly why BIS wrote the rule as a product of the two rather than as a raw TOPS cutoff: a cutoff on TOPS alone could be dodged by simply reporting a lower-precision number.
Both TPP values, 4,992, clear the first threshold (≥4,800), so the A100 is controlled outright: tpp_int8 > THRESHOLD_TPP prints True. As a cross-check, performance density is 4,992 ÷ 826 ≈ 6.04, which also clears the second clause (TPP≥1,600 and PD≥5.92): the chip is controlled twice over, by two independent tests that happen to agree. The program prints 4992 4992 True 6.04.
This is where the story gets interesting strategically. When the original October 2022 rule took effect, it flagged a chip using two separate criteria: a compute-performance cutoff, and, independently, a chip-to-chip interconnect (NVLink) bandwidth cutoff of 600 GB/s. Nvidia's response was the A800: identical GA100 compute die, same 624 TOPS and 312 TFLOPS, but NVLink bandwidth cut from the A100's 600 GB/s down to 400 GB/s. The H800 did the same to the H100, cutting NVLink from roughly 900 GB/s to 400 GB/s. Notice what the TPP formula in the code above does not take as an argument: interconnect bandwidth. Cutting NVLink speed changes nothing about tpp_int8 or tpp_fp16; it only mattered because the 2022 rule's interconnect-bandwidth clause was a separate, independently gameable trigger. Both chips sold briskly into China through most of 2023, marketed frankly as export-control-compliant. The October 2023 update closed exactly this gap: it dropped chip-to-chip interconnect bandwidth as a qualifying criterion entirely and rewrote control purely around TPP and performance density, both properties of the compute die itself. Since the A800/H800 die was never anything other than the full A100/H100 die, its TPP had been 4,992 (or the H800's equivalent) the entire time; once interconnect stopped being a way out, both chips became controlled.
A common misconception: export controls as a wall, not a toll
A natural assumption, once you have seen a gate this precise, is that clearing 4,800 TPP is like clearing a border wall: below it, an AI accelerator can reach China freely; above it, none can, full stop. That is wrong in a way that matters strategically. Export controls raise cost and impose delay; they do not impose an absolute technical ceiling on what a determined, well-resourced actor inside the restricted country can build domestically.
The clearest evidence is the Kirin 9000s processor inside Huawei's Mate 60 Pro, released in September 2023. Independent teardown analysis found it was fabricated by SMIC, China's leading foundry, on a process broadly comparable to a 7-nanometre node, the exact regime EUV lithography was built to serve, using deep ultraviolet (DUV) immersion lithography with multiple patterning: exposing the same layer several times with offset masks to draw finer features than a single DUV exposure could achieve on its own. SMIC has no EUV scanner; ASML does not sell it one. Multi-patterning is not a secret workaround, it is decades-old, publicly documented technique, but it is slower, lower-yielding, and far more expensive per good chip than a single EUV exposure would be. The lesson generalizes: a chokepoint control changes the price and the calendar of a rival's capability, and it can meaningfully slow the diffusion of the most advanced accelerators used for frontier-model training. It does not, on its own, freeze a well-funded state's semiconductor programme in place, and mistaking a toll for a wall leads to overconfident predictions about how fast a technology gap will actually widen.
Strategic competition as a game: why racing beats coordinating even when both sides know better
Chokepoint control is one lever states use against a rival. The other side of AI geopolitics is what states do with the compute they already have: how hard to push capability forward relative to safety testing, when facing a rival doing the same calculation. Stuart Armstrong, Nick Bostrom, and Carl Shulman formalized this in their 2016 paper "Racing to the Precipice: A Model of Artificial Intelligence Development" (AI & Society, 31(2), 201–206), which models competing AI developers each choosing how much caution to invest, and shows that competitive pressure systematically erodes safety investment, and that this erosion gets worse as the number of competing teams grows.
Here is a simplified two-player version of that logic, built to show the mechanism, not to reproduce their published numbers. Two states, each choosing to Race (push capability fast, cut corners on safety evaluation to capture a strategic lead) or Coordinate (invest proportionally in safety and slower, more careful deployment). Payoffs, in stylized strategic-value units:
Rival: Coordinate Rival: Race
You: Coordinate 6, 6 -2, 10
You: Race 10, -2 4, 4Read the logic the way a game theorist would: fix the rival's move, and ask whether you would ever regret choosing Race. If the rival Coordinates, you get 10 by Racing versus 6 by Coordinating: Race wins. If the rival Races, you get 4 by Racing versus -2 by Coordinating: Race still wins. Racing strictly dominates Coordinating for both players regardless of what the other does, so the unique Nash equilibrium is (Race, Race), with payoff (4, 4) to both. Yet (Coordinate, Coordinate) pays (6, 6): both states would do strictly better if they could commit to coordinating together. Racing is individually rational and collectively worse, the defining signature of a Prisoner's Dilemma, and formally: 10 > 6 > 4 > -2 satisfies T > R > P > S, and 2×6 = 12 exceeds 10 + (-2) = 8, confirming mutual coordination is the jointly efficient outcome that the equilibrium fails to reach. This is the mechanism Armstrong, Bostrom, and Shulman formalize with more competitors and continuous safety-investment choices: a race dynamic does not require any player to prefer recklessness, it only requires that falling behind a rival who is racing costs you more than the shared risk of racing costs you both, which is exactly the asymmetry compute chokepoints, chip bans, and "AI arms race" rhetoric all amplify by raising the stakes of falling behind.
India between two poles: compute access as tiered geopolitics
India's position illustrates why "AI geopolitics" cannot be reduced to a two-country US-China story. On 15 January 2025, the outgoing US administration issued the AI Diffusion Rule, which sorted essentially every country on earth into three tiers: close allies with unrestricted chip access, a middle tier facing aggregate compute caps unless individually licensed, and an adversary tier facing the existing China-style restrictions. India, despite being a security partner of the US in other domains (the Quad, defence technology cooperation), was placed in the middle tier, subject to caps on how much aggregate GPU compute Indian entities could import without individual case-by-case licensing. The rule never took effect: the incoming administration rescinded it on 13 May 2025, before its compliance deadline, arguing it would have strained relationships with dozens of non-adversary countries.
The rescission did not touch the China-specific 2022 and 2023 rules this chapter has walked through in detail; those remain in force independent of how Washington treats everyone else. What the episode demonstrates is structural: even a country the US export-control regime does not consider adversarial can be sorted into a compute-access hierarchy by a rule it had no part in writing, and that hierarchy can be redrawn entirely by a change of US administration, on a timeline India does not control. That is precisely the strategic exposure the IndiaAI Mission's compute pillar and India's separate ₹76,000 crore Semiconductor Mission (approved December 2021, funding fabrication capacity such as the Tata Electronics–PSMC facility under construction in Dholera, Gujarat, though at mature process nodes, not the sub-7nm nodes frontier AI accelerators require) are built to hedge against: not the ability to ignore the chokepoint entirely, which remains years away, but the ability to not be entirely at its mercy.
Active recall
Attempt each question before reading its answer.
- A newly announced accelerator ("Chip Z") reports dense INT8 throughput of 550 TOPS and has a die area of 700 mm². Compute its TPP and performance density. Is it controlled, and under which clause? Its designer then shrinks the die to 500 mm² without changing throughput, hoping to escape control. Does that work, and why or why not?
- In the Race/Coordinate payoff matrix, suppose international coordination talks reduce the cost of unilateral restraint, raising the "Coordinate while rival Races" payoff from -2 to +2. Does the Nash equilibrium change? Show the comparison that answers this.
- Why is data a structurally weaker lever for national AI-strategy control than compute, even though modern large language models are extremely data-hungry?
- A classmate claims the October 2023 export-control update made it technically impossible for China to produce any AI accelerator at a 7-nanometre-class process node. Is this correct? What real example corrects it?
- The AI Diffusion Rule that would have capped India's aggregate GPU imports was rescinded in May 2025. Explain why this episode mattered for India's compute strategy even though the rule was never meant to target India specifically.
Answer 1. TPP = 550 × 8 = 4,400. This is below the 4,800 outright threshold, so check the second clause: PD = 4,400 ÷ 700 ≈ 6.29, which clears both TPP≥1,600 and PD≥5.92, so Chip Z is controlled under the second clause even though it misses the first. Shrinking the die to 500 mm² does not help: TPP is unchanged at 4,400 (throughput did not change), so PD becomes 4,400 ÷ 500 = 8.8, which is further above the 5.92 cutoff, not below it. Performance density has area in the denominator, so shrinking the die while holding compute fixed makes the chip look more concentrated, not less; the "obvious" fix backfires precisely because it targets the wrong variable. Only lowering TPP (throughput) or growing the die without adding throughput would move the chip toward the exportable region, and the first defeats the product's purpose while the second is not something a rational designer would do.
Answer 2. No change. The equilibrium depends on Race strictly dominating Coordinate, which requires two comparisons: against a Coordinating rival, 10 > 6 must hold; against a Racing rival, 4 > (new S) must hold. Raising S from -2 to +2 only affects the second comparison, and 4 > 2 still holds, so Race still dominates in both cases and (Race, Race) with payoff (4,4) remains the unique Nash equilibrium. This is a useful, general point: only changes to T (the temptation payoff) or R (the mutual-coordination payoff) that flip T > R or P > S can move the equilibrium; softening the sucker's payoff S alone narrows the gap between racing and coordinating without closing it.
Answer 3. Data is non-rival (one party's use does not exclude another's), trivially duplicable at near-zero marginal cost, and largely drawn from public or easily mirrored sources, so no government can meter or interdict it at a border the way it can a serialized physical chip crossing a customs checkpoint. Compute is a manufactured, trackable, excludable object running through a supply chain with only a few chokepoints (EDA/IP, EUV lithography, leading-edge fabrication); a licensing authority can refuse to let a specific chip leave a specific factory. There is no equivalent physical checkpoint for a terabyte of training text.
Answer 4. Incorrect. The Kirin 9000s inside Huawei's Mate 60 Pro (September 2023) was fabricated by SMIC at a 7-nanometre-class node using deep ultraviolet (DUV) multi-patterning lithography, without any EUV scanner, since ASML does not sell EUV tools to China. Export controls raised the cost and lowered the yield of reaching that node domestically; they did not make it technically impossible. The correct framing is that chokepoint controls slow diffusion of the most advanced, highest-yield, lowest-cost accelerators and widen a capability-and-cost gap over time; they are a toll on the fastest path, not an absolute wall around the destination.
Answer 5. The rule mattered because it demonstrated that compute-access hierarchies are set externally and can shift abruptly. India, a non-adversary US partner, was still placed in a middle tier facing aggregate import caps under the January 2025 rule, and had that exposure removed only because a change in US administration rescinded the rule four months later, on a timeline India had no say in. Because the China-specific 2022/2023 controls stayed untouched throughout, the episode showed India that its AI compute access sits inside a regime it does not author and cannot fully predict, reinforcing the strategic logic behind building sovereign compute capacity (the IndiaAI Mission's GPU pool) and, longer-term, sovereign fabrication capacity (the Semiconductor Mission), even though the latter currently targets mature nodes far short of the sub-7nm silicon frontier AI training requires.
Think About It
Think about this: How would you explain ai in geopolitics: power dynamics and strategic competition to a friend who has never seen a computer? What real-world analogy would you use? Imagine you had to build a system using these concepts — what would be your first step? Try this: before moving on, write down three things you learned and one question you still have.
Key Takeaways — Summary and Recap
Let us recap what we covered: the core ideas behind ai in geopolitics: power dynamics and strategic competition, how they connect to real-world applications, and why they matter for your journey in computer science. Remember these key points as you move forward. For competitive exam preparation (CBSE, JEE, BITSAT), focus on understanding the WHY behind each concept, not just the WHAT.